1. Field of the Invention
The present invention relates to layout structure of a MOS transistor, and more particularly to layout structure of a horizontal MOS transistor.
2. Description of Related Art
A semiconductor device disclosed in JP Laid-open Patent publication No. 9-129867 intends to reduce ON resistance by shortening a distance between source contacts with respect to a horizontal DSA (Double-diffused Self Alignment system) power MOSFET. As shown in FIG. 9, unit cells of the semiconductor device is structured such that a drain contact 27 is arranged in a rectangular region surrounded by adjoining four source contacts 25 each of which is surrounded by gate layer 23 and periphery of the rectangular region is surrounded by gate layer 23. The drain contact 27 has four sizes parallel to diagonal lines of the rectangular region and is arranged facing source contacts 25 or arranged on the diagonal lines so that ON resistance can be reduced due to shortened distance between two contacts.